Title：A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations
Authors: Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue
Jounrnals：IEICE Technical Report (DC2007-2)
Volume: 107
Number: DC-17
Pages: 7-12
Published Month: 4
Published Year: 2007
Type: techreport
Abstract:
Soft errors refer to intermittent malfunctions, which are not physical defects.Due to the high speed and low voltage operation of VLSIs, soft errors caused by particle strikes on combinational logics cannot be disregarded, not just on memory elements. According to the model of soft errors presented in [1], focusing on the observation that a logic chain attenuates the noise caused by a particle strike on the logics, we propose a heuristic algorithm of scheduling in high-level synthesis for reducing the soft error rate. Several case studies show that the proposed algorithm can effectively reduce the soft error rate while achieving minimum latencies under resource constraints.
