Title:An optimization of thru trees for test generation based on acyclical testability

Authors: Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue

Jounrnals:Tech. Report of IEICE

Volume: 107

Number: 334

Pages: 13-18

Published Month: 11

Published Year: 2007

Type: techreport

The class of acyclic sequential circuits is $¥tau^2$-bounded, i.e., acyclic sequential circuits are practically easily testable¥cite{tau1}, ¥cite{tau2}. Further, classes of acyclically testable sequential circuits¥cite{acy} and extended acyclically testable ones¥cite{oka}, which are larger than that of acyclic sequential circuits, have been proposed. A key condition for acyclical / extended acyclical testability is defined mainly by means of thru functions, and hence, a given sequential circuit can be modified into such testable circuits by adding thru functions. Consequently, the DFT overhead can be reduced compared toconventional full scan design.This paper presents a method for implementing optimal thru trees which minimize the hardware cost required for extended acyclical testability of a given sequential circuits. We formulate the optimization problem on design for testability with thru trees based on extended acyclical testability, and express the formulation as an integer linear programming (ILP) model. Experimental results show the effectiveness of our formulation, and also demonstrate the effectiveness of the class of extended acyclical testability.

Reference: http://ci.nii.ac.jp/naid/110006533957