タイトル：A synthesis method to alleviate over-testing of delay faults based on RTL don't care path identification
著者: Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
雑誌名：VLSI test symposium (VTS09)
ページ: 71-76
発行月: 5
発行年: 2009
タイプ: inproceedings
