Title：A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application
Authors: Shigo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue
Jounrnals：IEICE Technical Report
Volume: 112
Number: 429
Pages: 49-54
Published Month: 2
Published Year: 2013
Type: techreport
Abstract:
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limits, of LSIs for such applications are tolerable. In this paper, we focus on logic optimization of circuits for error tolerant applications[10-12]. In the previous method, to identify removable portions of a logic circuit, the acceptability of stuck-at faults in the circuit is checked by utilizing threshold test generation algorithm, even though this acceptability identification is time-consuming[12]. To accelerate of this acceptability identification, we propose an acceptability identification procedure based on necessary assignments requires for detecting unacceptable faults. Discussing the relationship between multiple acceptable faults and necessary assignmetns, we present an algorithm, which is faster than the test-generation-based previous algorithm, to check the acceptability of faults with implication procedure. Experimental results show that the proposed algorithm can reduce the computation effort to identify acceptable faults.
Reference: http://www.ieice.org/ken/paper/20130213FB1g/
