タイトル：Logic Simplification by Minterm Complement for Error Tolerant Application
著者: Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue
アブストラクト: Error tolerant applications can tolerate specific errors, whose frequency and/or severity are within certain limits. This error tolerability is greatly instrumental in simplifying logic circuits for such applications. In this paper, we propose a logic simplification method for error tolerant application. Owing to error tolerance, we have an opportunity to complement several minterms of a given logic function within a threshold; if appropriate minterms are selected to be complemented, the given function can be greatly simplified. To select such minterms, we focus on two transformations, expansion and reduction, of prime implicants of the given logic function, and discuss the effect of the transformations on logic simplification. The proposed algorithm utilizing such transformations can efficiently find effective minterm complement. Experimental results show that, compared with a previous method, which employs only expansion of prime implications, the proposed algorithm can produce smaller logic circuits with reasonable computational effort.