Transactions & Journals: 46 papers

  1. Toya Kani, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Design of Fully Stochastic Computing Neurons Focused on the Gain of Sigmoid Functions," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J104-D, No. 7, 2021.
  2. Hideyuki Ichihara, Ryoga Mizobata, Mitsuyoshi Ashida, Tomoo Inoue, "A Design of Multipliers with Approximate Adders and Compensators According to the Accuracy Required for Applications," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J104-D, No. 7, 2021.
  3. Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines," IEICE Trans. Fundamentals, Vol. E103-A, No. 12, pp. 1464-1471, 2020.
  4. Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Digital Filters Based on Stochastic Computing," Trans. on Emerging Topics in Comp., Sep 2016.
  5. Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "Concurrent Testable Response Analyzer with Cyclic Code in Built-in Self Test," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J95-D, No. 3, pp. 496-505, 2012.
  6. Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue, "Hybrid Test Application in Partial Skewed-load Scan Design," IEICE Trans. Fundamentals, Vol. E94-A, No. 12, pp. 2571-2578, Dec. 2011.
  7. Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko, "Flexible test scheduling for an asynchronous on-chip interconnect through special data transfer," IEICE Trans. on Fundamentals, Vol. E94-A, No. 12, pp. 2563-2570, Dec. 2011.
  8. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Backward-data-direction clocking and relevant optimal register assignment in datapath synthesis," IEICE Trans. Fundamentals, Vol. E94-A, No. 4, pp. 1067-1081, Apr. 2011.
  9. Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, "A Practical Threshold Test Generation for Error Tolerant Application," IEICE Trans. Inf. & Syst., Vol. E93-D, No. 10, pp. 2776-2782, Oct. 2010.
  10. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Design and Optimization of Transparency-Based TAM for SoC Test," IEICE Trans. Inf. & Syst., Vol. E93-D, No. 6, pp. 1549-1559, June 2010.
  11. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Test Generation for Sequential Circuits with Partial Thru Testability," IEICE Trans. Inf. & Syst., Vol. J92-D, No. 12, Dec. 2009.
  12. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Optimal register assignment with minimum-path delay compensation for variation-aware datapaths," IEICE Trans. Fundamentals, Vol. E92-A, No. 4, pp. 1096-1105, Apr. 2009.
  13. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Novel register sharing in datapath for structural robustness against delay variation," IEICE Trans. on Fundamentals, Vol. E91-A, No. 4, pp. 1044-1053, Apr. 2008.
  14. Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara, "A Self-Test of Dynamically Reconfigurable Processors with Test Frames," IEICE Trans. Inf. & Syst., Vol. E91, No. 3, pp. 756-762, Mar. 2008.
  15. Hideyuki Ichihara, Tomoyuki Saiki, Tomoo Inoue, "An Architecture of Embedded Decompressor with Reconfigurability for Test Compression," IEICE Trans. Inf. & Syst., Vol. E91, No. 3, pp. 713-719, Mar. 2008.
  16. Hideyuki Ichihara, Toshimasa Ohara, Michihiro Shintani, Tomoo Inoue, "A Variable-length Coding Adjustable for Compressed Test Application," IEICE Trans. Inf. & Syst., Vol. E90, No. 8, pp. 1235-1242, Aug. 2007.
  17. Hideyuki Ichihara, T. Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita, "A Statistical Error Model for the Image Sensor and Its Testing," IEICE Trans. Inf. & Syst., Vol. J89-D, No. 8, pp. 1663-1672, Aug. 2006.
  18. Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue, "An Adaptive Decompressor for Test Application with Variable-Length Coding," IPSJ Journal, Vol. 47, No. 6, pp. 1639-1647, June 2006.
  19. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," IEICE Trans. Inf. & Syst., Vol. E89-D, No. 6, pp. 1931-1939, June 2006.
  20. Nobuya Oka, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of a Scheduling Algorithm in High-Level Synthesis for Acyclic Partial Scan," , pp. 41-44, ? 2005.
  21. Hideyuki Ichihara, Tomoo Inoue, "A Test Generation for Compressible and Compact Test Sets," IEICE Trans. D-I, Vol. J88-D-I, No. 6, pp. 1021-1028, June 2005.
  22. Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue, "Huffman-Based Test Response Coding," IEICE Trans. Inf. & Syst., Vol. E88-D, No. 1, pp. 158-161, Jan. 2005.
  23. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A design scheme for delay testing of controllers using state transition information," IEICE Trans. Fundamentals, Vol. E87-A, No. 12, pp. 3200-3207, Dec. 2004.
  24. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu, "Test Cost Reduction for Logic Circuits -Reduction of test data volume and testing time-," IEICE Trans. D-I, Vol. J87-D-I, No. 3, pp. 291-307, Mar. 2004.
  25. Hideyuki Ichihara, Tomoo Inoue, "A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG," IEICE Trans. Fundamentals, Vol. E86-A, No. 12, pp. 3072-3078, Dec. 2003.
  26. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A test generation method for delay faults in sequential circuits with discontinuous reconvergence structure," Trans. of IEICE (DI), Vol. J86-D-I, No. 12, pp. 872-883, Dec. 2003.
  27. Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura, "Test Generation for Test Compression Based on Statistical Coding," IEICE Trans. Inf. & Syst., Vol. E85-D, No. 10, pp. 1466-1473, Oct. 2002.
  28. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Processing Order for Obtaining Implication Relations in Static Learning," IEICE Trans. Inf. & Syst., Vol. E83-D, No. 10, pp. 1908-1911, Oct. 2000.
  29. Chiiho Sano, Takahiro Mihara, Tomoo Inoue, D. K. Das, Hideo Fujiwara, "A partial scan design method for sequential circuits with hold registers," IEICE Trans. of IEICE(DI), Vol. J83-D-I, No. 9, pp. 981-990, Sept. 2000.
  30. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "A binding method in high-level synthesis for testable datapaths based on acyclic partial scan design," Trans. of IEICE(DI), Vol. J83-D-I, No. 2, pp. 282-292, Feb. 2000.
  31. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Test Pattern Selection with A Limited Number of Tests," IEICE Trans. D-I, Vol. J82-D-I, No. 7, pp. 861-868, July 1999.
  32. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara, "Test sequence compaction methods for acyclic sequential circuits using a time expansion model," Trans. of IEICE (DI), Vol. J82-D-I, No. 7, pp. 869-878, Jul 1999.
  33. Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, Tomoo Inoue, Hideo Fujiwara, "Testing for the programming circuit of SRAM-based FPGAs," IEICE Trans. Inf. & Syst., Vol. E82-D, No. 6, pp. 1051-1057, June 1999.
  34. Hideyuki Ichihara, Kozo Kinoshita, "Logic Optimization: Redundancy Addition and Removal Using Implication Relations," IEICE Trans. Inf. and Syst., Vol. E81-D, No. 7, pp. 724-730, July 1998.
  35. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "Partial scan design methods based on internally balanced structure," Trans. of IEICE(DI), No. 3, pp. 318-327, Mar. 1998.
  36. Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara, "Universal fault diagnosis for lookup table FPGAs," IEEE Design & Test of Computers, Vol. 15, No. 1, pp. 39-44, Jan. 1998.
  37. Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Trans.of IPSJ, Vol. 38, No. 5, pp. 1040-1049, May 1997.
  38. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Invariant Implication Relations for Removing Partial Circuits," Trans. of IEICE D-I, Vol. J79-D-I, No. 12, pp. 1037-1045, Dec. 1996.
  39. Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, Tomoo Inoue, Hideo Fujiwara, "Testing of configurable logic blocks in a look-up table FPGA," Trans. of IEICE (DI), Vol. J79-D-I, No. 12, pp. 1141-1150, Dec. 1996.
  40. Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara, "On the synthesis of synchronizable finite state machines with partial scan," Trans. of IEICE (DI), Vol. J79-D-I, No. 12, pp. 1046-1054, Dec. 1996.
  41. Tomoo Inoue, Takashi Fujii, Hideo Fujiwara, "Performance analysis of parallel test generation for combinational circuits," IEICE Trans. on Information and Systems, Vol. E79-D, No. 9, pp. 1257-1265, Sept. 1996.
  42. Tomoo Inoue, H. Maeda, Hideo Fujiwara, "On the effect of scheduling in test generation," IEICE Trans. on Information and Systems, Vol. E79-D, No. 8, pp. 1190-1197, Aug. 1996.
  43. Hideo Fujiwara, Tomoo Inoue, "Optimal granularity and scheme of parallel test generation in a distributed system," IEEE Trans. on Parallel and Distributed Systems, Vol. 6, No. 7, pp. 677-686, July 1995.
  44. Tomoo Inoue, Tomoki Yonezawa, Hideo Fujiwara, "Optimal granularity of parallel test generation on the Client-Agent-Server model," Trans. of Information Processing Society of Japan, Vol. 35, No. 8, pp. 1614-1623, Aug. 1994.
  45. Tomoo Inoue, Tomoki Yonezawa, Hideo Fujiwara, "An optimal scheme of parallel processing for test generation in a distributed system," Trans. of IEICE(DI), Vol. J76-D-I, No. 11, pp. 604-612, Nov. 1993.
  46. Hideo Fujiwara, Tomoo Inoue, "Optimal granularity of test generation in a distributed system," IEEE Trans. on Computer-Aided Design, No. 8, pp. 885-892, Aug. 1990.

Surveys & Columns: 3 papers

  1. Tomoo Inoue, "Defect and Test Technology of Integrated Circuits," The Journal of Institute of Electronics, Information and Communication Engineers, Vol. 103, No. 1, pp. 62-67, 2020.
  2. Tomoo Inoue, "A high-level approach to test design," Session 7: Testing, SEMI Technology Symposium 2008, 2008.
  3. Toshinori Hosokawa, Tomoo Inoue, "Design for testability at RT level design of LSIs," IEICE Information and Systems Society Journal, Vol. 8, No. 4, pp. 6-8, 2004.

Proceedings of International Conferences/Symposiums/Workshops (peer reviewed): 112 papers

  1. Hideyuki Ichihara, Tomohiro Adachi , Tomoo Inoue, "Experimental Evaluation of the No-Reference Test Based of False Edge Detection for Image Processing Application," Digest of Papers 21th IEEE Workshop on RTL and High Level Testing, 2020.
  2. Tomoo Inoue, Kazunori Yukihiro, Hideyuki Ichihara, "Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems," Digest of Papers 20th IEEE Workshop on RTL and High Level Testing (WRTLT '19), 2019.
  3. Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue, "State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines," IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019.
  4. Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis," Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19), pp. 55-60, 2019.
  5. Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Effective Utilization of Register-Transfer Paths Based on Enhancing Multiplexer Functions in RTL Scan Design," Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18), pp. 1-6, Oct 2018.
  6. Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits," Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17), pp. 1-6, Nov 2017.
  7. Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "State Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines," Proc. ITC-Asia, Sep 2017.
  8. Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Impact of State Assignment on Error Resilient Stochastic Computing with Linear Finite State Machines," Digest of Papers 17th IEEE Workshop on RTL and High Level Testing , Nov 2016.
  9. Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue, "Exploration of Four-Phase Dual-Rail Asynchronous RTL Design for Delay-Robustness," Digest of Papers 17th IEEE Workshop on RTL and High Level Testing , Nov 2016.
  10. Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Stochastic Number Generation with Internal Signals of Logic Circuits," Proc. SASIMI, Oct 2016.
  11. Tsuyoshi Iwagaki, Syoichi Ohmoto, Hideyuki Ichihara, Tomoo Inoue, "A Prototype of a Hardware SAT Solver for Similar Large Instances and Its Application to Test Generation," Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (WRTLT '15), Nov 2015.
  12. Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue, "Logic Simplification by Minterm Complement for Error Tolerant Application," Porc. ICCD, pp. 102-108, Oct 2015.
  13. Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue, "Designing area-efficient controllers for multi-cycle transient fault tolerant systems," Proc. 20th IEEE European Test Symposium (ETS '15), May 2015.
  14. Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue, "A practical approach for logic simplification based on fault acceptability for error tolerant application," Proc. 20th IEEE European Test Symposium (ETS '15), May 2015.
  15. Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "A Fault Tolerant Response Analyzer with Self-Error-Correction Capability," Proc. European Test Symp., May 2015.
  16. Tsuyoshi Iwagaki, Yutaro Ishimori, Tatsuya Nakaso, Hideyuki Ichihara, Tomoo Inoue, "A controller design in high-level synthesis for long duration transient fault tolerance," Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (WRTLT '14), Nov. 2014.
  17. Hideyuki Ichihara, Daiki Sunamori, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Stochastic Circuits with Shared Random Number Sources," Proc. IEEE International Conference on Computer Design, pp. 361-366, Oct 2014.
  18. Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue, "A scheduling algorithm in datapath synthesis for long duration transient fault tolerance," Proc. 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '14), pp. 128--133, Oct. 2014.
  19. Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A System-Error-Rate-Oriented Approach to Test Generation for Effective Yield Maximization," IEEE International Workshop on Reliability Aware System Design and Test, Jan. 2014.
  20. Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-test," Proc. 22nd IEEE Asian Test Symp., Nov. 2013.
  21. Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Error Correctable Response Analyzers for Reliable Built-in Self-test," Digest of Papers 14th IEEE Workshop on RTL and High Level Testing, Nov. 2013.
  22. Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue, "A Heuristic Algorithm for Operational Unit Binding to Synthesize Multi-Cycle Transient Fault Tolerant Datapaths," Digest of Papers 14th IEEE Workshop on RTL and High Level Testing, Nov. 2013.
  23. Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue, "Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool," Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 615--618, Dec. 2012.
  24. Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Error Correctable Test Pattern Generator for Reliable Built-in Self Test ," Workshop on RTL and High Level Testing, Nov. 2012.
  25. Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, Kewal K. Saluja, "Exact and Heuristic Methods of Generating Compact Tests for Hold-time Violations," Workshop on RTL and High Level Testing, Nov. 2012.
  26. Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue, "Modeling Economics of LSI Design and Manufacturing for Test Design Selection," Proc. ICCD, Oct. 2012.
  27. Kenji Ueda, Fumiyuki Hafuri, Toshiya Mukai, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A technique for SAT-based test generation through history of reusing solutions," Proc. 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI ’12), pp. 197-198, Mar. 2012.
  28. Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue, "Test Compression Based on Lossy Image Encoding," IEEE Asian Test Symp. (ATS), pp. 273-278, Nov. 2011.
  29. Tsuyoshi Iwagaki, Fumiyuki Hafuri, Kenji Ueda, Toshiya Mukai, Hideyuki Ichihara, Tomoo Inoue, "An approach to hardware SAT solvers for test generation based on instance similarity," 12th IEEE Workshop on RTL and High Level Testing, pp. 69-74, Nov. 2011.
  30. Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, "High-Level Synthesis for Multi-Cycle Transient Fault Tolerant Datapaths," Proc. IEEE Int. On-Line Testing Symp. (IOLTS), pp. 13-18, July 2011.
  31. Tsuyoshi Iwagaki, Kewal K. Saluja, "Power-constrained test generation for hold-time faults using integer linear programming," Proc. 4th IEEE International Workshop on Impact of Low-Power Design on Test and Reliability (LPonTR '11), pp. 1-2, May 2011.
  32. Tsuyoshi Iwagaki, Kewal K. Saluja, "Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations," Proc. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '11), pp. 175-178, Apr. 2011.
  33. Seiji Hirota, Ke Wang, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Experimental Evaluation of Hybrid RTL Scan Design," Workshop on RTL and High Level Testing, Dec. 2010.
  34. Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A New Class of Acyclically Testable Sequential Circuits with Multiplexers," Workshop on RTL and High Level Testing, Dec. 2010.
  35. Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko, "An approach to test scheduling for asynchronous on-chip interconnects using integer programming," Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10), pp. 69-74, Dec. 2010.
  36. Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Design of Response Analyzers with Self-Distinguishability in Built-in Self-Test ," International Symposium on Communications and Information Technologies (ISCIT), pp. 732-735, Oct. 2010.
  37. Takehiro Mikami, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Utilization of False Paths for Area/Delay Optimization in Logic Synthesis," FIT2010, Vol. 9, No. 1, pp. 59-64, 2010.
  38. Noboru Shimizu, Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Repairable Test Generator in Built-in Self Test," FIT2010, Vol. 9, No. 1, pp. 109-114, 2010.
  39. Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "An FPGA-Based Fail-soft System with Adaptive Reconfiguration," 16th IEEE International On-Line Testing Symposium, pp. 127-132, July 2010.
  40. Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue, "Hybrid Test Application in Hybrid Delay Scan Design," IEEE Proc. ETS, pp. 247, May 2010.
  41. Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko, "Test scheduling algorithms for delay-insensitive chip area interconnects based on cone partitioning," Proc. 3rd International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR '10), pp. 1-2, May 2010.
  42. Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, "A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic," IEEE Proc. DELTA, pp. 345-349, Jan. 2010.
  43. Hideyuki Ichihara, Yujiro Amano, Yuki Yoshikawa, Tomoo Inoue, "A Yield Model of Design for Testability and Repairability," IEEE Proc. RASDAT, pp. 23-28, Jan. 2010.
  44. Tsuyoshi Iwagaki, Mineo Kaneko, "A pseudo-boolean technique for generating compact transition tests with all-output-propagation properties," Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA '10), pp. 293-296, Jan. 2010.
  45. Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, "A Practical Approach to Threshold Test Generation for Error Tolerant Circuits," IEEE Proc. ATS, Nov. 2009.
  46. Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Design of Concurrently Testable Response Analyzers in Built-in Self-Test," IEEE Digest Papers of WRTLT, pp. 88-93, Nov. 2009.
  47. Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Reliability and Performance Analysis of FPGA-Based Fault Tolerant System," IEEE Proc. DFTS, pp. 245-253 , Oct. 2009.
  48. Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Test Data Reduction by Test Point Insertion Based on Necessary Assignment," Proc. European Test Symposium (CD-ROM), 2009.
  49. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Test Generation and DFT Based on Partial Thru Testability," Proc. European Test Symposium (CD-ROM), May 2009.
  50. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara, "A synthesis method to alleviate over-testing of delay faults based on RTL don't care path identification," VLSI test symposium (VTS09), pp. 71-76, May 2009.
  51. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Safe clocking for the setup and hold timing constraints in datapath synthesis," Proc. 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09), pp. 27-32, May 2009.
  52. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "A conjecture on the number of extra registers in safe clocking-based register assignment," Proc. 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '09), pp. 131-136, Mar. 2009.
  53. Tsuyoshi Iwagaki, Mineo Kaneko, "On the derivation of a minimum test set in high quality transition testing," Proc. IEEE Latin-American Test Workshop (LATW '09), pp. 1-6, Mar. 2009.
  54. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara, "Fast False Path Identification Based on Functional Unsensitizability Using RTL Information," Proc. the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 660-665, Jan. 2009.
  55. Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Reliability and Performance of FPGA-Based Fault Tolerant Systems," Digest of Papers of 9th Workshop on RTL and High-Level Testing (WRTLT'08), pp. 75-80, Nov. 2008.
  56. Hideyuki Ichihara, Kazuko Hiramoto, Yuki Yoshikawa, Tomoo Inoue, "A Method for Test Data Reduction by Test Point Insertion Based on Necessary Assignment," Digest of Papers of 9th Workshop on RTL and High-Level Testing(WRTLT'08), pp. 105-110, 2008.
  57. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Safe clocking register assignment in datapath synthesis," Proc. IEEE International Conference on Computer Design (ICCD '08), pp. 120-127, Oct. 2008.
  58. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Minimizing minimum delay compensations for timing variation-aware datapath synthesis," Proc. IEEE Mid-West Symposium on Circuits and Systems (MWSCAS '08), pp. 97-100, Aug. 2008.
  59. Tsuyoshi Iwagaki, Satoshi Ohtake, "Generation of power-constrained scan tests and its difficulty," Proc. IEEE International Design and Test Workshop (IDT '07), pp. 71-76, Dec. 2007.
  60. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara, "Efficient path delay test generation based on stuck-at test generation using checker circuitry," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07), pp. 418-423, Nov. 2007.
  61. Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue, "Test Compression / Decompression Based on JPEG VLC Algorithm," Proc. Asian Test Symposium, pp. 87-90, Oct. 2007.
  62. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Extended Class of Acyclically Testable Circuits," Dig. of Papers of 8th Workshop on RTL and High-Level Testing (WRTLT'07), Oct. 2007.
  63. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Structural robustness of datapaths against delay-variations," Proc. 14th Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI '07), pp. 272-279, Oct. 2007.
  64. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "TAM Design and Optimization for Transparency-based SoC Test," Proc. VLSI Test Symp., pp. 381-386, May 2007.
  65. Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara, "Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors," Proc. European Test Symp., pp. 117-122, May 2007.
  66. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Optimal Test Bus Design for Transparency-based SoC Test," Workshop on RTL and High Level Testing, pp. 21-26, Nov. 2006.
  67. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A new test generation model for broadside transition testing of partial scan circuits," Proc. 14th IFIP/IEEE/ACM International Conference on Very Large Scale Integration (VLSI-SoC '06), pp. 308-313, Oct. 2006.
  68. Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "A Reconfigurable Embedded Decompressor for Test Compression," Proc. IEEE International Workshop on Electronic Design, Test & Applications (DELTA2006), pp. 301-306, Jan. 2006.
  69. Hideyuki Ichihara, Naoki Okamoto, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "An Effective Design for Hierarchical Test Generation Based on Strong Testability," Proc. IEEE Asian Test Symposium, pp. 288-293, Dec. 2005.
  70. Kazuko Kambe, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara, "Efficient constraint extraction for template-based processor self-test generation," Proc. 14th IEEE Asian Test Symposium (ATS '05), pp. 444-447, Dec. 2005.
  71. Tomoo Inoue, Yudai Kawahara, Hideyuki Ichihara, "A method for designing hierarchically testable datapaths based on fixed-control testability," Workshop on RTL and High Level Testing, pp. 174-179, July 2005.
  72. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," Digest of Papers 6th IEEE Workshop on RTL and High Level Testing (WRTLT '05), pp. 184-191, July 2005.
  73. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation," Proc. 10th IEEE European Test Symposium (ETS '05), pp. 48-53, May 2005.
  74. Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, "A Huffman-based coding with efficient test application," Proc. ASP-DAC, pp. 75-78, Jan. 2005.
  75. Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue, "A Test Decompression Scheme for Variable-Length Coding," IEEE Proc. Asian Test Symp., pp. 426-431, Nov. 2004.
  76. Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, "A Test Compression Algorithm for Reducing Test Application Time," 5th Workshop on RTL and High Level Testing, pp. 53-58, Nov. 2004.
  77. D. K. Das, Tomoo Inoue, S. Chakraborty, Hideo Fujiwara, "Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity," IEEE Proc. Asian Test Symp., pp. 342-347, Nov. 2004.
  78. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A design methodology to realize delay testable controllers using state transition information," Proc. 9th IEEE European Test Symposium (ETS '04), pp. 168-173, May 2004.
  79. Hideyuki Ichihara, Michihiro Shintani, Toshimasa Ohara, Tomoo Inoue, "Test Response Compression Based on Huffman Coding," Proc. Asian Test symposium, pp. 446-449, Nov. 2003.
  80. Tomoo Inoue, Naoki Okamoto, Hideyuki Ichihara, Toshinori Hosokawa, Hideo Fujiwara, "An Improvement of a Test Plan Generation Algorithm for Hierarchical Test Based on Strong Testability," Workshop on RTL and High Level Testing, pp. 37-42, Nov. 2003.
  81. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "An approach to non-scan design for delay fault testability of controllers," Digest of Papers 4th IEEE Workshop on RTL and High Level Testing (WRTLT '03), pp. 79-85, Nov. 2003.
  82. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "Reducibility of sequential test generation to combinational test generation for several delay fault models," Proc. 12th IEEE Asian Test Symposium (ATS '03), pp. 58-63, Nov. 2003.
  83. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A path delay test generation method for sequential circuits based on reducibility to combinational test generation," Digest of Papers 8th IEEE European Test Workshop (ETW '03), pp. 307-312, May 2003.
  84. Hideyuki Ichihara, Tomoo Inoue, "Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG," Proc. DATE03, pp. 1180-1181, Mar. 2003.
  85. Hideyuki Ichihara, Kozo Kinoshita, Kohji Isodono, Shigeki Nishikawa, "Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs," Proc. the 16th International Conference on VLSI Design, pp. 329-334, Jan. 2003.
  86. Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara, "A scheduling method in high-level synthesis for acyclic partial scan design," Proc. 11th IEEE Asian Test Symposium, pp. 128-133, Nov. 2002.
  87. Tomoo Inoue, Hideo Fujiwara, "A partial scan design with orthogonal scan paths," 3rd Workshop on RTL and High Level Testing, Nov. 2002.
  88. Hideyuki Ichihara, Tomoo Inoue, "Generating Small Test Sets for Test Compression / Decompression Using Statistical Coding," The First International Workshop on Electronic Design, Test & Applications, pp. 396-400, Jan. 2002.
  89. Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara, "A scheduling method in high-level synthesis for RTL acyclic partial scan design," 2nd Workshop on RTL ATPG and DFT, Nov. 2001.
  90. Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura, "Dynamic Test Compression Using Statistical Coding," The Tenth Asian Test Symposium, pp. 143-148, ? 2001.
  91. Tomoo Inoue, D. K. Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara, "Test generation for acyclic sequential circuits with hold registers," Proc. International Conf. on Computer Aided Design, pp. 550-556, Nov. 2000.
  92. Tomoo Inoue, D. K. Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara, "Test generation and design-for-testability based on acyclic structure with hold registers," 1st Workshop on RTL ATPG and DFT, Sept. 2000.
  93. Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, S. M. Reddy, "Test Transformation to improve Compaction by Statistical Encoding," The VLSI Design 2000 Conference, pp. 294-299, Jan. 2000.
  94. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On An Effective Selection of IDDQ Measurement Vectors for Sequential Circuits," The Eighth Asian Test Symposium, pp. 147-152, Nov. 1999.
  95. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara, "Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time exp," Proc. 8th IEEE Asian Test Symp., pp. 192-199, Nov. 1999.
  96. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "A high-level synthesis approach to partial scan design based on acyclic structure," Proc. 8th IEEE Asian Test Symp., pp. 309-314, Nov. 1999.
  97. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On test generation with a Limited Number of Tests," Proc. Ninth Great Lakes Symposium on VLSI, pp. 12-15, Mar. 1999.
  98. Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara, "An optimal time expansion model based on combinational ATPG for RT level circuits," Proc. IEEE the 7th Asian Test Symp., pp. 190-197, Dec. 1998.
  99. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "Partial scan design methods based on internally balanced structure," Proc. Asia and South Pacific Design Automation Conference, pp. 211-216, Feb. 1998.
  100. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identif," Proc. The Seventh Asian Test Symposium, pp. 58-63, ? 1998.
  101. Hideyuki Ichihara, Kozo Kinoshita, "On Acceleration of Logic Circuit Optimization Using Implication Relations," Proc. The Sixth Asian Test Symposium, pp. 222-227, Dec. 1997.
  102. Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara, "On the complexity of universal fault diagnosis for Look-up table FPGAs," Proc. Sixth IEEE Asian Test Symp., pp. 276-281, Nov. 1997.
  103. Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, Tomoo Inoue, Hideo Fujiwara, "Testing for the programming circuit of LUT-based FPGAs," Proc. Sixth IEEE Asian Test Symp., pp. 242-247, Nov. 1997.
  104. Tomoo Inoue, Hideo Fujiwara, "Sequential test generation based on circuit pseudo-transformation," Proc. Sixth IEEE Asian Test Symp., Nov 1997.
  105. Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara, "An approach to the synthesis of synchronizable finite state machines with partial scan," Proc. 1996 IEEE Asian Test symposium, pp. 130-135, Nov. 1996.
  106. Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, Tomoo Inoue, Hideo Fujiwara, "A test methodology for interconnect structures of LUT-based FPGAs," Proc. Fifth IEEE Asian Test symposium, pp. 68-74, Nov. 1996.
  107. Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, "Universal test complexity of field-programmable gate arrays," Proc. fourth IEEE Asian Test Symposium, pp. 259-265, Nov. 1995.
  108. Tomoo Inoue, H. Maeda, Hideo Fujiwara, "A scheduling problem in test generation," Proc. IEEE VLSI Test Symposium, pp. 344-349, Apr. 1995.
  109. Tomoo Inoue, Takashi Fujii, Hideo Fujiwara, "On the performance analysis of parallel processing for test generation," Proc. 3rd IEEE Asian Test Symposium, pp. 69-74, Nov. 1994.
  110. Tomoo Inoue, Tomoki Yonezawa, Hideo Fujiwara, "An optimal scheme of parallel processing for test generation in a distributed system," Proc. 2nd IEEE Asian Test Symposium, pp. 8-13, Nov. 1993.
  111. Hideo Fujiwara, Tomoo Inoue, "Analysis of parallel processing for test generation in a distributed system," Dig. 1989 Joint Symp. on Fault Tolerant Computing, pp. 128-133, Nov. 1989.
  112. Hideo Fujiwara, Tomoo Inoue, "Optimal granularity of test generation in a distributed system," Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 158-161, ? 1989.

Technical Reports of Domestic Workshops): 151 papers

  1. Mitsuyoshi Ashida, Ryoga Mizobata, Hideyuki Ichihara, Tomoo Inoue, "An Experimental Consideration of a Hybrid Approximate Multiplier Design According to the Accuracy Required for Applications," The 22nd IEEE Hiroshima Section Student Symposium, 2020.
  2. Toya Kani, Nobuaki Seto, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On the Accuracy of Sigmoid Functions in Stochastic-Computing-Based Neural Networks," DA Symposium, pp. 36-43, 2020.
  3. Toya Kani, Nobuaki Seto, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Study on Hardware Implementation of Sigmoid Functions with Stochastic Computing," FTC Workshop, 2020.
  4. Norishige Morikawa, Yuri Aono, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Simplification of Multiple-Output Logic Functions for Error-Tolerant Applications Using Don't-Care Extension," FTC workshop, 2020.
  5. Kazunori Yukihiro, Hideyuki Ichihara, Tomoo Inoue, "Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems," Tech. Repo., pp. 31-36, 2019.
  6. Hideyuki Ichihara, Yuki Maeda, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Transient Fault Tolerant Design for Stochastic Circuits with Linear Finite State Machines," Functional Integrated Information System, 2019.
  7. Ryoga Mizobata, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Multipliers with Approximate Full Adders and Compensators for the Required Accuracy of Applications," IEICE Technical Report (FIIS-19-494), pp. 1-6, Mar 2019.
  8. Hideyuki Ichihara, "Benefits and Challenges of Stochastic Computing Circuits," Proc. IFAT, 2019.
  9. Yuki Maeda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines ," Tech. Repo., pp. 61-66, 2019.
  10. Toya Kani, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Study on the Accuracy of Stochastic Operation for Neural Networks Using Positive/Negative Separation of Products and Approximation of Sigmoid Functions," FTC Technical Report, 2019.
  11. Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis," IEICE Technical Report (DC2018-45), Vol. 118, No. 335, pp. 137-142, Dec 2018.
  12. Hideyuki Ichihara, "BENEFITS AND CHALLENGES OF STOCHASTIC COMPUTING CIRCUITS," Proc. of the 2018 IEICE Society Conference, pp. SS25-26, Sep 2018.
  13. Kazunori Yukihiro, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Performance Degradation Faults of Autonomous Cars Using MATLAB/Simulink," FIIS, Mar 2018.
  14. Akira Kojima, Naoki Ishikawa, Hideyuki Ichihara, Hiroyuki Inoue, Tomoyuki Ohta, Hiroyasu Obata, Atsushi Kubota, Koichi Shin, Chisa Takano, Shinobu Nagayama, "Development of Experimental Robot and Laboratory Curriculum for Education of Embedded Technology and Network Technology," Proc. 80th National Convention of IPSJ, pp. 373-374, 2018.
  15. Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "An Improved Algorithm of Peripheral Signal Selection for Stochastic Number Generation," FTC , Jan 2018.
  16. Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "On Fault Detectability by Scan Chain Testing in RTL Scan Design," FTC Technical Report, Jan 2018.
  17. Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits," IEICE Tech. Repo., vol. 117, no. 273, VLD2017-47, pp. 115-120, Nov 2017.
  18. Akira Kojima, Naoki Ishikawa, Hideyuki Ichihara, Hiroyuki Inoue, Tomoyuki Ohta, Hiroyasu Obata, Atsushi Kubota, Koichi Shin, Chisa Takano, Shinobu Nagayama, "Development of Experimental Robot for Education of Embedded Technology and Network Technology," 6th workshop , 2017.
  19. Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "Detection of faults on functional paths in RTL scan circuits by scan chain testing," FIIS-17-461, pp. 1-4, 2017.
  20. Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application ," IEICE Tech. Repo., vol. 116, no. 478, VLD2016-128, pp. 145-150, Mar 2017.
  21. Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Architecture of Multiply-Accumulate Operation with Stochastic Iteration ," IEICE Tech. Repo., vol. 116, no. 478, VLD2016-130, pp. 157-162, Mar 2017.
  22. Seiya Kawashima, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "On a Design of Arithmetic Circuits with Multiple Accuracy Modes and Their Application," Tech. Repo. FIIS, Mar 2017.
  23. So Shioyama, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Implementation of Mutually Reconfigurable Fault-Tolerant Systems with Zynq SoCs," Tech. Repo. FIIS, Mar 2017.
  24. Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue, "Impact of operational unit binding on aging-induced degradation in high-level synthesis for asynchronous systems," IEICE Technical Report (DC2016-78), Vol. 116, No. 466, pp. 23-28, Feb 2017.
  25. Maki Fujiha, Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Random Sequence Generation with Internal Signals of Logic Circuits for Stochastic Computing," FTC workshop, Jan 2017.
  26. Motoi Fukuda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On State Assignment of Finite State Machines for Soft Error Resilient Stochastic Computing," IEICE technical report, pp. 7-12, Jun 2016.
  27. Yasutake Mitoh, Seiya Kawashima, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Design and Implementation of Adaptive Cruise Control Systems Based on a Cyber-Physical Model," Tech. Repo. FIIS, Mar 2016.
  28. Yutaro Ishimori, Seiya Kawashima, Yasutake Mitoh, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "On modeling of cyber-physical systems with dependability," Tech. Repo. FIIS, Mar 2016.
  29. Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Random Sequences with Internal Signals of Logic Circuits for Stochastic Number Generation," Proc. the IEICE General Conference, Mar 2016.
  30. Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences," IEICE Tech. Repo., vol. 115, no. 449, DC2015-89, pp. 19-24, Feb 2016.
  31. Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Stochastic Circuits with Shared Random Number Sources," ACSI, Jan 2016.
  32. Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems ," IEICE Tech. Repo., vol. 115, no. 339, DC2015-56, pp. 147-152, Dec 2015.
  33. Motoi Fukuda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Influence of Logical Stuck-at Faults on Accuracy in Stochastic Computing," FTC, Jul 2015.
  34. Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On Accuracy and Area of Digital Filter Circuits Based on Stochastic Computing," Functional Integrated Information System, Jun 2015.
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  44. Daiki Sunamori, Takuya Ohishi, Shota Ishii, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "FPGA-based Implementation of Image Processing with Stochastic Computing," Tech. Repo. FIIS, Nov 2013.
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  46. Junpei Kamei, Shigo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A logic simplification algorithm with multiple stuck-at faults for error tolerant application ," IEICE Technical Report (VLD2012-136), Vol. 112, No. 451, pp. 1-6, Mar. 2013.
  47. Tomoya Inaoka, Junpei Kamei, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A study on logic simplification of bus inverting circuits for low power," IEICE Technical Report (FIIS-13-353), pp. 1-6, Mar. 2013.
  48. Shigo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application ," IEICE Technical Report, Vol. 112, No. 429, pp. 49-54, Feb. 2013.
  49. Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse," IEICE Technical Report (DC2012-80), Vol. 112, No. 429, pp. 1-6, Feb. 2013.
  50. Masaaki Sakurada, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Model for Over-testing Alleviation and Its Application to Testing Based on Fault Acceptability," Tech. Report of IEICE, Vol. 112, No. 362, pp. 21-26, Dec. 2012.
  51. Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis," IEICE Technical Report (DC2012-50), Vol. 112, No. 321, pp. 147-152, Nov. 2012.
  52. Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse," IEICE Technical Report (DC2012-49), Vol. 112, No. 321, pp. 141-146, Nov. 2012.
  53. Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test," Tech. Report of IEICE, Vol. 112, No. 102, pp. 15-20, June 2012.
  54. Junpei Kamei, Shigo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "An efficient procedure of acceptability identification for logic optimization based on acceptable faults," IEICE Technical Report (FIIS-12-337), pp. 1-6, June 2012.
  55. Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools," IEICE Technical Report (VLD2012-130), Vol. 111, No. 450, pp. 61-66, Mar. 2012.
  56. Kouta Omobayashi, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Low-Power Color Interporation Circuits Based on Color Difference ," IEICE Technical Report (VLD2012-143), Vol. 111, No. 450, pp. 139-144, Mar. 2012.
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  59. Fumiyuki Hafuri, Kenji Ueda, Toshiya Mukai, Hideyuki Ichihara, Tomoo Inoue, "Test Generation Using Boolean Satisfiability Based on Instance Similarity," 13th IEEE Hiroshima Student Symposium, pp. 373-376, Nov. 2011.
  60. Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Modeling Economics of LSI Design and Manufacturing for Selecting Test Design," IEICE Technical Report (DC2011-47), Vol. 111, No. 325, pp. 115-120, Nov 2011.
  61. Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "Effective multi-cycle signatures in testable response analyzers ," IEICE Tech. Rep., Vol. 111, No. 100, pp. 5-10, June 2011.
  62. Tsuyoshi Iwagaki, Kewal K. Saluja, "On indirect detection of functional hold-time violations using scan shift operations," IEICE Technical Report (FIIS-11-298), pp. 1-5, Mar. 2011.
  63. Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders ," Technical Report of IEICE, Vol. 110, No. 317, pp. 43-48, Nov. 2010.
  64. Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths ," IEICE Tech. Rep., Vol. 110, No. 317, pp. 25-30, Nov. 2010.
  65. Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue, "A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths," IEICE Tech. Rep., Vol. 110, No. 106, pp. 13-18, June 2010.
  66. Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Class of Partial Thru Testable Sequential Circuits with Multiplexers," IEICE Tech. Rep., Vol. 110, No. 106, pp. 7-11, June 2010.
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  68. Takumi Miyaguchi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, , "A Study on Acceptable Faults in Digital Filters," IEICE Tech. Repo., Vol. 109, No. 416, pp. 63-68, Feb. 2010.
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  70. Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Yield Model with Testability and Repairabilit," IEICE Technical Report, Vol. 109, No. DC-316 , pp. 89-94, Dec. 2009.
  71. Tsuyoshi Iwagaki, Mineo Kaneko, "A heuristic approach to detecting transition faults at all circuit outputs," Proc. IEICE Society Conference, pp. 54, Sept. 2009.
  72. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Resource sharing and scheduling algorithms against variation of control timings," IEICE Technical Report (VLD2009-10), July 2009.
  73. Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing," IEICE Technical Report, Vol. 109, No. 95, pp. 13-18, June 2009.
  74. Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A design of testable response analyzers in built-in self-test," IEICE Tech. Repo., Vol. 109, No. 11, pp. 37-42, 2009.
  75. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Safe clocking based datapath synthesis for the setup and hold timing constraints," 22nd Workshop on Circuits and Systems in Karuizawa, pp. 432-437, Apr. 2009.
  76. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Adjustable safe clocking and relevant register assignment in datapath synthesis," IEICE Technical Report (VLD2008-130), pp. 23-28, Mar. 2009.
  77. Yusuke Nakashima, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "On the Acceleration of Threshold Test Generation Based on Fault Acceptability," IEICE Technical Report, Vol. 108, No. 431, pp. 1-6, Feb. 2009.
  78. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "A note on the number of extra registers in safe clocking-based register assignment," IEICE Technical Report (CAS2008-90), pp. 147-152, Jan. 2009.
  79. Kenta Sutoh, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Model for Threshold Testing," IEICE Tech. Rep., Vol. 108, No. 352, pp. 5-10, Dec. 2008.
  80. Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment," IEICE Tech. Rep., Vol. 108, No. 299, pp. 121-126, Nov. 2008.
  81. Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance," IEICE Tech. Rep., Vol. 108, No. 299, pp. 127-132, Nov. 2008.
  82. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Delay variability-aware datapath synthesis based on safe clocking for setup and hold timing constraints," IEICE Technical Report (VLD2008-85), pp. 151-156, Nov. 2008.
  83. Tsuyoshi Iwagaki, Mineo Kaneko, "An integer programming for generating high quality transition tests," IEICE Technical Report (DC2008-29), pp. 7-12, Nov. 2008.
  84. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, "Delay variation-aware datapath synthesis based on register clustering," IEICE Technical Report (VLD2008-51), pp. 25-30, Sept. 2008.
  85. (NO DISPLAYABLE DATA)
  86. (NO DISPLAYABLE DATA)
  87. Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Study on Reliability and Performance of FPGA-Based Fault Tolerant Systems," IEICE Technical Report, Vol. 108, No. 15, pp. 19-24, Apr. 2008.
  88. (NO DISPLAYABLE DATA)
  89. (NO DISPLAYABLE DATA)
  90. Hirotaka Shiomichi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Synthesis of Fault Secure Datapaths with DFG Restructuring," IEICE Tech. Repo., No. 482, pp. 51-56, Feb. 2008.
  91. (NO DISPLAYABLE DATA)
  92. Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "An optimization of thru trees for test generation based on acyclical testability," Tech. Report of IEICE, Vol. 107, No. 334, pp. 13-18, Nov. 2007.
  93. (NO DISPLAYABLE DATA)
  94. Tsuyoshi Iwagaki, Satoshi Ohtake, "An approach to power-constrained test generation for scan circuits," IEICE Technical Report (FIIS-07-218), pp. 1-6, Oct. 2007.
  95. Tsuyoshi Iwagaki, Satoshi Ohtake, "Analysis of fault coverage under a power budget in scan testing," Proc. IEICE Society Conference, pp. 53, Sept. 2007.
  96. Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue, "A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations," IEICE Technical Report (DC2007-2), Vol. 107, No. DC-17, pp. 7-12, Apr. 2007.
  97. (NO DISPLAYABLE DATA)
  98. Syota Takahashi, Ryoji Noji, Hideyuki Ichihara, Tomoo Inoue, "An optimal set of backup contexts for reliable FPGA systems," Proc. the 69th National Convention of IPSJ, No. 1, pp. 109-110, Mar. 2007.
  99. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Entended Class of Sequential Circuits with Acyclical Testability," IEICE Tech. Repo. (DC2006-88), Vol. 106, No. 528, pp. pp.49-54, Feb. 2007.
  100. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara, "A test generation framework using checker circuits and its application to path delay test generation," IEICE Technical Report (CAS2006-76), Vol. 106, No. 512, pp. 37-42, Jan. 2007.
  101. Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue, "A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure," IEICE Tech. Rep. (DC2006-42), Vol. 106, No. 390, pp. 23-28, Nov. 2006.
  102. Yukinori Setohara, Yusuke Nakashima, Hideyuki Ichihara, Tomoo Inoue, "Test Compression/Decompression with the Decoding Function in Multimedia Cores," IEICE Tech. Repo.(DC2006-43), Vol. 106, No. 390, pp. 29-34, Nov. 2006.
  103. Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue, "A Self-Test of Dynamically Reconfigurable Processors," IEICE Tech. Repo. (DC2006-49), Vol. 106, No. 390, pp. 65-70, Nov. 2006.
  104. (NO DISPLAYABLE DATA)
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  106. Masashi Yamanaka, Hideyuki Ichihara, Tomoo Inoue, "On the Fault Escape and Yield Loss by Faulty BIST Circuits," Proc. of the 2006 IEICE General Conference, Mar. 2006.
  107. Go Handa, Naoya Takeuchi, Hideyuki Ichihara, Tomoo Inoue, "A register binding method in high level synthesis for strong testability," IEICE Tech. Rep., Vol. DC2005-72, pp. 1-6, Feb. 2006.
  108. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A broadside test generation method for transition faults in partial scan circuits," IEICE Technical Report (DC2005-54), Vol. 105, No. 443, pp. 7-12, Dec. 2005.
  109. Yukinori Setohara, Takashi Fujii, Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of Fault Simulation Using FPGAs," , pp. 238-241, Nov. 2005.
  110. Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue, "An Improvement of a DFT Method Based on Fixed-control Testability by Conflict Avoidance," FIT2005, Sept. 2005.
  111. Nobuya Oka, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of a Scheduling Algorithm in High-Level Synthesis for Acyclic Partial Scan," FIT2005, Sept. 2005.
  112. Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "A Reconfigurable Embedded Decompressor for LSI Testing ," , Vol. 105, No. 42, pp. 1-6, May 2005.
  113. Eitaro Kohno, Kaori Maeda, Tomoo Inoue, Toshiaki Kitamura, Noriyuki Iwane, Nobuo Suematsu, "A case study of construction of a campus network ofr academic activity," IPSJ SIG Technical Report, Vol. 2005-DSM-3, No. 11, pp. 61-66, Mar. 2005.
  114. Naoki Okamoto, Hideyuki Ichihara, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "Design for Hierarchical Testability for Reducing Hold Controls," Technical Report of IEICE, Vol. 104, No. 664, pp. 15-20, Feb. 2005.
  115. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "Equivalence of sequential transition test generation and constrained combinational stuck-at test generation," IEICE Technical Report (DC2004-96), Vol. 104, No. 664, pp. 27-32, Feb. 2005.
  116. Kenichi Yukumatsu, Syun Matsumoto, Yoshinori Matsuura, Tomoo Inoue, "On a representation of a two sex model describing population distribution based on reaction-diffusion equations systems," Technical Report of IEICE, Vol. 104, No. 583, pp. 51-56, Jan. 2005.
  117. Michihiro Shintani, Masakuni Ochi, Hideyuki Ichihara, Tomoo Inoue, "A decompressor with buffer for test compression / decompression," Technical Report of IEICE, Vol. ICD2004, No. 213, pp. 35-40, Jan. 2005.
  118. Masakuni Ochi, Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, "A Test Vector Ordering for Overhead Reduction of Test Decompressors," Technical report of IEICE, Vol. 103, No. 668, pp. 41-46, Feb. 2004.
  119. Kenichi Yukumatsu, Yoshinori Matsuura, Tomoo Inoue, "A model of population dynamics with non-linear convective reaction-diffusion equations," IEEE HISS, pp. 235-238, Dec. 2003.
  120. Naoki Okamoto, Hideyuki Ichihara, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "An Improvement of the Test Plan Generation Algorithm for Strongly Testable Datapaths," Technical Report of IEICE, Vol. 103, No. 476, pp. 13-18, Nov. 2003.
  121. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "A method of design for delay fault testability of controllers," IEICE Technical Report (DC2003-38), Vol. 103, No. 476, pp. 25-30, Nov. 2003.
  122. Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, "A Test Decompression Scheme Based on Huffman Coding," Proc Electronics, Information and Systems Conference, pp. 602-608, Aug. 2003.
  123. Toshimasa Ohara, Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "A Test Compression for Test Application Based on Huffman Coding," Technical Report of IEICE, Vol. 102, No. 658, pp. 67-72, Feb. 2003.
  124. Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "Test response compression using Huffman coding," Technical Report of IEICE, Vol. VLD2002-88, pp. 35-40, Nov. 2002.
  125. (NO DISPLAYABLE DATA)
  126. (NO DISPLAYABLE DATA)
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  128. (NO DISPLAYABLE DATA)
  129. Tomokazu Miura, Tomoo Inoue, Akio Tamura, Hideo Fujiwara, "A scheduling method in high-level synthesis for partial scan design based on acyclic structure," Technical Report of IEICE, No. VLD2001-10, pp. 109-114, Nov. 2001.
  130. Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "Test Generation for Acyclic Sequential Circuits using Combinational ATPG for Single Stuck-at Faults," Technical Report of IEICE, Vol. 100, No. 473, pp. 203-208, Nov. 2000.
  131. Y. Otsubo, Tomoo Inoue, Y. Fukui, Hideo Fujiwara, "On the acceleration of test application time for microcontrollers using embedded processors," Technical Report of IPSJ, No. (DA91-4), pp. 25-32, Feb. 1999.
  132. Chiiho Sano, Tomoo Inoue, D. K. Das, Hideo Fujiwara, "A partial scan design method for sequential circuits with hold registers," Technical Report of IPSJ, pp. 43-50, Feb. 1999.
  133. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "High-level synthesis for testable data paths based on cycle-breaking partial scan design," Technical Report of IEICE, No. (FTS98-114, pp. 65-72, Dec. 1998.
  134. Hideyuki Ichihara, Kozo Kinoshita, "New Redundancy Identification Method on Logic Optimization Using Implication Relation," Technology Reports of Osaka University, Vol. 48, No. 2301-2318, pp. 55-63, Apr. 1998.
  135. Takahiro Mihara, Tomoo Inoue, Hideo Fujiwara, "A test generation method for acyclic sequential circuits with L/H-type registers," Technical Report of IEICE, No. (FTS97-75), pp. 33-40, Feb. 1998.
  136. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara, "On the test sequence compaction for acyclic sequential circuits using time-expansion model," Technical Report of IEICE, pp. 147-154, ? 1998.
  137. Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Trans. of IPSJ, Vol. 96, No. 5, pp. 9-16, May 1997.
  138. Hideyuki Ichihara, Kozo Kinoshita, "On Acceleration of Logic Circuits Optimization using Implication Relations," Technical Report of IEICE, Vol. 96, No. 519, pp. 57-64, Feb. 1997.
  139. Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "An RT level partial scan design method based on combinational ATPG," Technical Report of IEICE, No. (FTS96-67), pp. 73-80, Feb. 1997.
  140. Kohji Yamasaki, Tomoo Inoue, Hideo Fujiwara, "Parallel processing for sequential test generation based on state parallelism," Technical Report of IEICE, pp. 89-96, Feb. 1997.
  141. Satoshi Miyazaki, Tomoo Inoue, Hideo Fujiwara, "The complexity of fault diagnosis for look-up table field-programmable gate arrays," Technical Report of IEICE, Vol. 96, No. 291(FTS96-, pp. 17-24, Oct. 1996.
  142. Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Technical Report of IEICE, Vol. 96, No. 291 (FTS96, pp. 9-16, Oct. 1996.
  143. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara, "Extended partial scan design capable of combinational test generation," Technical Report of IEICE, Vol. 96, No. 291, pp. 1-8, Oct. 1996.
  144. Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara, "On the synthesis of synchronizable finite state machines with partial scan," Technical Report of IEICE, Vol. 95, No. 309 (FTS95, pp. 31-38, Oct. 1995.
  145. Hiroyuki Michinishi, Tokumi Yokohira, T. Okamoto, Tomoo Inoue, Hideo Fujiwara, "Testing of look-up table FPGAs," Technical Report of IEICE, pp. 49-56, June 1995.
  146. Takashi Fujii, Tomoo Inoue, Hideo Fujiwara, "Performance evaluation of parallel processing for test generation," Technical Report of IEICE, Vol. 94, No. 492 (FTS94, pp. 25-32, Feb. 1995.
  147. H. Maeda, Tomoo Inoue, Hideo Fujiwara, "On a scheduling problem in test generation," Technical Report of IEICE, Vol. 94, No. 492 (FTS94, pp. 39-46, Feb. 1995.
  148. Tomoo Inoue, Takashi Fujii, Hideo Fujiwara, "On the performance analysis of parallel processing for test generation," Technical Report of IEICE, Vol. 93, No. 459, pp. 39-46, Feb. 1994.
  149. Tomoo Inoue, Hideo Fujiwara, "On the test set size in parallel test generation," Technical Report of IEICE, Vol. 93, No. 303, pp. 1-8, Oct. 1993.
  150. Tomoo Inoue, Tomoki Yonezawa, Hideo Fujiwara, "An optimal scheme of parallel processing for test generation in a distributed system," Technical Report of IEICE, Vol. 92, No. 283, pp. 17-24, Oct. 1992.
  151. Tomoo Inoue, Hideo Fujiwara, "Optimal schedule in parallel processing for test pattern generation," Technical Report of IEICE, Vol. 89, No. 249, pp. 59-64, Oct. 1989.