Search results of query **"ichihara"**

**Transactions & Journals**: **26** papers

- Naoki Okuda, Kaori Maeda, Chisa Takano, Hideyuki Ichihara, "On the Estimation of Multi-Cloud Computational Resources Based on the Analysis Methodology of Inventory Systems," IEICE Trans. Communications (Japanese Edition), No. 2, pp. 63-71, 2024.
- Naoki Okuda, Kaori Maeda, Chisa Takano, Hideyuki Ichihara, "An Effectiveness Evaluation the DDoS Mitigation Method Based on Diffusion Flow Control," IPSJ Journal, Vol. 69, No. 3, 2022.
- Toya Kani, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Design of Fully Stochastic Computing Neurons Focused on the Gain of Sigmoid Functions," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J104-D, No. 7, 2021.
- Hideyuki Ichihara, Ryoga Mizobata, Mitsuyoshi Ashida, Tomoo Inoue, "A Design of Multipliers with Approximate Adders and Compensators According to the Accuracy Required for Applications," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J104-D, No. 7, 2021.
- Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines," IEICE Trans. Fundamentals, Vol. E103-A, No. 12, pp. 1464-1471, 2020.
- Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Digital Filters Based on Stochastic Computing," Trans. on Emerging Topics in Comp., Sep 2016.
- Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "Concurrent Testable Response Analyzer with Cyclic Code in Built-in Self Test," IEICE Trans. Inf.& Syst.(Japanese Edition), Vol. J95-D, No. 3, pp. 496-505, 2012.
- Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue, "Hybrid Test Application in Partial Skewed-load Scan Design," IEICE Trans. Fundamentals, Vol. E94-A, No. 12, pp. 2571-2578, Dec. 2011.
- Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, "A Practical Threshold Test Generation for Error Tolerant Application," IEICE Trans. Inf. & Syst., Vol. E93-D, No. 10, pp. 2776-2782, Oct. 2010.
- Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Design and Optimization of Transparency-Based TAM for SoC Test," IEICE Trans. Inf. & Syst., Vol. E93-D, No. 6, pp. 1549-1559, June 2010.
- Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Test Generation for Sequential Circuits with Partial Thru Testability," IEICE Trans. Inf. & Syst., Vol. J92-D, No. 12, Dec. 2009.
- Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara, "A Self-Test of Dynamically Reconfigurable Processors with Test Frames," IEICE Trans. Inf. & Syst., Vol. E91, No. 3, pp. 756-762, Mar. 2008.
- Hideyuki Ichihara, Tomoyuki Saiki, Tomoo Inoue, "An Architecture of Embedded Decompressor with Reconfigurability for Test Compression," IEICE Trans. Inf. & Syst., Vol. E91, No. 3, pp. 713-719, Mar. 2008.
- Hideyuki Ichihara, Toshimasa Ohara, Michihiro Shintani, Tomoo Inoue, "A Variable-length Coding Adjustable for Compressed Test Application," IEICE Trans. Inf. & Syst., Vol. E90, No. 8, pp. 1235-1242, Aug. 2007.
- Hideyuki Ichihara, T. Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita, "A Statistical Error Model for the Image Sensor and Its Testing," IEICE Trans. Inf. & Syst., Vol. J89-D, No. 8, pp. 1663-1672, Aug. 2006.
- Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue, "An Adaptive Decompressor for Test Application with Variable-Length Coding," IPSJ Journal, Vol. 47, No. 6, pp. 1639-1647, June 2006.
- Nobuya Oka, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of a Scheduling Algorithm in High-Level Synthesis for Acyclic Partial Scan," , pp. 41-44, ? 2005.
- Hideyuki Ichihara, Tomoo Inoue, "A Test Generation for Compressible and Compact Test Sets," IEICE Trans. D-I, Vol. J88-D-I, No. 6, pp. 1021-1028, June 2005.
- Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue, "Huffman-Based Test Response Coding," IEICE Trans. Inf. & Syst., Vol. E88-D, No. 1, pp. 158-161, Jan. 2005.
- Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu, "Test Cost Reduction for Logic Circuits -Reduction of test data volume and testing time-," IEICE Trans. D-I, Vol. J87-D-I, No. 3, pp. 291-307, Mar. 2004.
- Hideyuki Ichihara, Tomoo Inoue, "A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG," IEICE Trans. Fundamentals, Vol. E86-A, No. 12, pp. 3072-3078, Dec. 2003.
- Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura, "Test Generation for Test Compression Based on Statistical Coding," IEICE Trans. Inf. & Syst., Vol. E85-D, No. 10, pp. 1466-1473, Oct. 2002.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Processing Order for Obtaining Implication Relations in Static Learning," IEICE Trans. Inf. & Syst., Vol. E83-D, No. 10, pp. 1908-1911, Oct. 2000.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Test Pattern Selection with A Limited Number of Tests," IEICE Trans. D-I, Vol. J82-D-I, No. 7, pp. 861-868, July 1999.
- Hideyuki Ichihara, Kozo Kinoshita, "Logic Optimization: Redundancy Addition and Removal Using Implication Relations," IEICE Trans. Inf. and Syst., Vol. E81-D, No. 7, pp. 724-730, July 1998.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On Invariant Implication Relations for Removing Partial Circuits," Trans. of IEICE D-I, Vol. J79-D-I, No. 12, pp. 1037-1045, Dec. 1996.

**Proceedings of International Conferences/Symposiums/Workshops (peer reviewed)**: **72** papers

- Tamaki Kozuma, Qiling Wang, Hideyuki Ichihara, Tomoo Inoue, "Reliability Analysis of Approximate Multipliers with Recovery Schemes," IEEE Proc. Asian Test Symposium, 2023.
- Hideyuki Ichihara, Naruki Itoh, Tomoo Inoue, "An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application," Proc. ITC-Asia, 2022.
- Hideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue, "A Design of Approximate Voting Schemes for Fail-Operational Systems," IEEE Proc. Asian Test Symposium, 2021.
- Hideyuki Ichihara, Takayuki FUKUDA, Tomoo Inoue, "A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing," IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021.
- Hideyuki Ichihara, Tomohiro Adachi , Tomoo Inoue, "Experimental Evaluation of the No-Reference Test Based of False Edge Detection for Image Processing Application," Digest of Papers 21st IEEE Workshop on RTL and High Level Testing, 2020.
- Tomoo Inoue, Kazunori Yukihiro, Hideyuki Ichihara, "Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems," Digest of Papers 20th IEEE Workshop on RTL and High Level Testing (WRTLT '19), 2019.
- Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue, "State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines," IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019.
- Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis," Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19), pp. 55-60, 2019.
- Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Effective Utilization of Register-Transfer Paths Based on Enhancing Multiplexer Functions in RTL Scan Design," Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18), pp. 1-6, Oct 2018.
- Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits," Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17), pp. 1-6, Nov 2017.
- Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "State Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines," Proc. ITC-Asia, Sep 2017.
- Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Impact of State Assignment on Error Resilient Stochastic Computing with Linear Finite State Machines," Digest of Papers 17th IEEE Workshop on RTL and High Level Testing , Nov 2016.
- Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue, "Exploration of Four-Phase Dual-Rail Asynchronous RTL Design for Delay-Robustness," Digest of Papers 17th IEEE Workshop on RTL and High Level Testing , Nov 2016.
- Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Stochastic Number Generation with Internal Signals of Logic Circuits," Proc. SASIMI, Oct 2016.
- Tsuyoshi Iwagaki, Syoichi Ohmoto, Hideyuki Ichihara, Tomoo Inoue, "A Prototype of a Hardware SAT Solver for Similar Large Instances and Its Application to Test Generation," Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (WRTLT '15), Nov 2015.
- Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue, "Logic Simplification by Minterm Complement for Error Tolerant Application," Porc. ICCD, pp. 102-108, Oct 2015.
- Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue, "Designing area-efficient controllers for multi-cycle transient fault tolerant systems," Proc. 20th IEEE European Test Symposium (ETS '15), May 2015.
- Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue, "A practical approach for logic simplification based on fault acceptability for error tolerant application," Proc. 20th IEEE European Test Symposium (ETS '15), May 2015.
- Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "A Fault Tolerant Response Analyzer with Self-Error-Correction Capability," Proc. European Test Symp., May 2015.
- Tsuyoshi Iwagaki, Yutaro Ishimori, Tatsuya Nakaso, Hideyuki Ichihara, Tomoo Inoue, "A controller design in high-level synthesis for long duration transient fault tolerance," Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (WRTLT '14), Nov. 2014.
- Hideyuki Ichihara, Daiki Sunamori, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Stochastic Circuits with Shared Random Number Sources," Proc. IEEE International Conference on Computer Design, pp. 361-366, Oct 2014.
- Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue, "A scheduling algorithm in datapath synthesis for long duration transient fault tolerance," Proc. 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '14), pp. 128--133, Oct. 2014.
- Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A System-Error-Rate-Oriented Approach to Test Generation for Effective Yield Maximization," IEEE International Workshop on Reliability Aware System Design and Test, Jan. 2014.
- Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-test," Proc. 22nd IEEE Asian Test Symp., Nov. 2013.
- Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Error Correctable Response Analyzers for Reliable Built-in Self-test," Digest of Papers 14th IEEE Workshop on RTL and High Level Testing, Nov. 2013.
- Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue, "A Heuristic Algorithm for Operational Unit Binding to Synthesize Multi-Cycle Transient Fault Tolerant Datapaths," Digest of Papers 14th IEEE Workshop on RTL and High Level Testing, Nov. 2013.
- Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue, "Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool," Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 615--618, Dec. 2012.
- Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Error Correctable Test Pattern Generator for Reliable Built-in Self Test ," Workshop on RTL and High Level Testing, Nov. 2012.
- Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, Kewal K. Saluja, "Exact and Heuristic Methods of Generating Compact Tests for Hold-time Violations," Workshop on RTL and High Level Testing, Nov. 2012.
- Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue, "Modeling Economics of LSI Design and Manufacturing for Test Design Selection," Proc. ICCD, Oct. 2012.
- Kenji Ueda, Fumiyuki Hafuri, Toshiya Mukai, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A technique for SAT-based test generation through history of reusing solutions," Proc. 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI ’12), pp. 197-198, Mar. 2012.
- Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue, "Test Compression Based on Lossy Image Encoding," IEEE Asian Test Symp. (ATS), pp. 273-278, Nov. 2011.
- Tsuyoshi Iwagaki, Fumiyuki Hafuri, Kenji Ueda, Toshiya Mukai, Hideyuki Ichihara, Tomoo Inoue, "An approach to hardware SAT solvers for test generation based on instance similarity," 12th IEEE Workshop on RTL and High Level Testing, pp. 69-74, Nov. 2011.
- Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, "High-Level Synthesis for Multi-Cycle Transient Fault Tolerant Datapaths," Proc. IEEE Int. On-Line Testing Symp. (IOLTS), pp. 13-18, July 2011.
- Seiji Hirota, Ke Wang, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Experimental Evaluation of Hybrid RTL Scan Design," Workshop on RTL and High Level Testing, Dec. 2010.
- Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A New Class of Acyclically Testable Sequential Circuits with Multiplexers," Workshop on RTL and High Level Testing, Dec. 2010.
- Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Design of Response Analyzers with Self-Distinguishability in Built-in Self-Test," International Symposium on Communications and Information Technologies (ISCIT), pp. 732-735, Oct. 2010.
- Takehiro Mikami, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Utilization of False Paths for Area/Delay Optimization in Logic Synthesis," FIT2010, Vol. 9, No. 1, pp. 59-64, 2010.
- Noboru Shimizu, Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Repairable Test Generator in Built-in Self Test," FIT2010, Vol. 9, No. 1, pp. 109-114, 2010.
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "An FPGA-Based Fail-soft System with Adaptive Reconfiguration," 16th IEEE International On-Line Testing Symposium, pp. 127-132, July 2010.
- Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue, "Hybrid Test Application in Hybrid Delay Scan Design," IEEE Proc. ETS, pp. 247, May 2010.
- Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, "A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic," IEEE Proc. DELTA, pp. 345-349, Jan. 2010.
- Hideyuki Ichihara, Yujiro Amano, Yuki Yoshikawa, Tomoo Inoue, "A Yield Model of Design for Testability and Repairability," IEEE Proc. RASDAT, pp. 23-28, Jan. 2010.
- Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, "A Practical Approach to Threshold Test Generation for Error Tolerant Circuits," IEEE Proc. ATS, Nov. 2009.
- Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Design of Concurrently Testable Response Analyzers in Built-in Self-Test," IEEE Digest Papers of WRTLT, pp. 88-93, Nov. 2009.
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Reliability and Performance Analysis of FPGA-Based Fault Tolerant System," IEEE Proc. DFTS, pp. 245-253 , Oct. 2009.
- Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Test Data Reduction by Test Point Insertion Based on Necessary Assignment," Proc. European Test Symposium (CD-ROM), 2009.
- Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "Test Generation and DFT Based on Partial Thru Testability," Proc. European Test Symposium (CD-ROM), May 2009.
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Reliability and Performance of FPGA-Based Fault Tolerant Systems," Digest of Papers of 9th Workshop on RTL and High-Level Testing (WRTLT'08), pp. 75-80, Nov. 2008.
- Hideyuki Ichihara, Kazuko Hiramoto, Yuki Yoshikawa, Tomoo Inoue, "A Method for Test Data Reduction by Test Point Insertion Based on Necessary Assignment," Digest of Papers of 9th Workshop on RTL and High-Level Testing(WRTLT'08), pp. 105-110, 2008.
- Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue, "Test Compression / Decompression Based on JPEG VLC Algorithm," Proc. Asian Test Symposium, pp. 87-90, Oct. 2007.
- Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Extended Class of Acyclically Testable Circuits," Dig. of Papers of 8th Workshop on RTL and High-Level Testing (WRTLT'07), Oct. 2007.
- Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "TAM Design and Optimization for Transparency-based SoC Test," Proc. VLSI Test Symp., pp. 381-386, May 2007.
- Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara, "Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors," Proc. European Test Symp., pp. 117-122, May 2007.
- Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Optimal Test Bus Design for Transparency-based SoC Test," Workshop on RTL and High Level Testing, pp. 21-26, Nov. 2006.
- Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "A Reconfigurable Embedded Decompressor for Test Compression," Proc. IEEE International Workshop on Electronic Design, Test & Applications (DELTA2006), pp. 301-306, Jan. 2006.
- Hideyuki Ichihara, Naoki Okamoto, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "An Effective Design for Hierarchical Test Generation Based on Strong Testability," Proc. IEEE Asian Test Symposium, pp. 288-293, Dec. 2005.
- Tomoo Inoue, Yudai Kawahara, Hideyuki Ichihara, "A method for designing hierarchically testable datapaths based on fixed-control testability," Workshop on RTL and High Level Testing, pp. 174-179, July 2005.
- Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, "A Huffman-based coding with efficient test application," Proc. ASP-DAC, pp. 75-78, Jan. 2005.
- Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue, "A Test Decompression Scheme for Variable-Length Coding," IEEE Proc. Asian Test Symp., pp. 426-431, Nov. 2004.
- Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, "A Test Compression Algorithm for Reducing Test Application Time," 5th Workshop on RTL and High Level Testing, pp. 53-58, Nov. 2004.
- Hideyuki Ichihara, Michihiro Shintani, Toshimasa Ohara, Tomoo Inoue, "Test Response Compression Based on Huffman Coding," Proc. Asian Test symposium, pp. 446-449, Nov. 2003.
- Tomoo Inoue, Naoki Okamoto, Hideyuki Ichihara, Toshinori Hosokawa, Hideo Fujiwara, "An Improvement of a Test Plan Generation Algorithm for Hierarchical Test Based on Strong Testability," Workshop on RTL and High Level Testing, pp. 37-42, Nov. 2003.
- Hideyuki Ichihara, Tomoo Inoue, "Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG," Proc. DATE03, pp. 1180-1181, Mar. 2003.
- Hideyuki Ichihara, Kozo Kinoshita, Kohji Isodono, Shigeki Nishikawa, "Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs," Proc. the 16th International Conference on VLSI Design, pp. 329-334, Jan. 2003.
- Hideyuki Ichihara, Tomoo Inoue, "Generating Small Test Sets for Test Compression / Decompression Using Statistical Coding," The First International Workshop on Electronic Design, Test & Applications, pp. 396-400, Jan. 2002.
- Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura, "Dynamic Test Compression Using Statistical Coding," The Tenth Asian Test Symposium, pp. 143-148, ? 2001.
- Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, S. M. Reddy, "Test Transformation to improve Compaction by Statistical Encoding," The VLSI Design 2000 Conference, pp. 294-299, Jan. 2000.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On An Effective Selection of IDDQ Measurement Vectors for Sequential Circuits," The Eighth Asian Test Symposium, pp. 147-152, Nov. 1999.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "On test generation with a Limited Number of Tests," Proc. Ninth Great Lakes Symposium on VLSI, pp. 12-15, Mar. 1999.
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita, "An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identif," Proc. The Seventh Asian Test Symposium, pp. 58-63, ? 1998.
- Hideyuki Ichihara, Kozo Kinoshita, "On Acceleration of Logic Circuit Optimization Using Implication Relations," Proc. The Sixth Asian Test Symposium, pp. 222-227, Dec. 1997.

**Technical Reports of Domestic Workshops)**: **94** papers

- Tomofumi Oda, Tomoo Inoue, Hideyuki Ichihara, "A Study on the Improvement of Fail-Operability in an Automotive System with the Approximate Voting Scheme E-IDMR," FIIS Tech. Repo., 2024.
- Qiling Wang, Hideyuki Ichihara, Tomoo Inoue, "A Study on Test Generation for Alleviating Over-testing of Approximate Multipliers ," IEICE Tech. Repo., pp. 17-22, 2024.
- Yo Muneta, Shinobu Nagayama, Hideyuki Ichihara, Tomoo Inoue, "An Attempt on ``Integration of Instruction and Evaluation'' Using Morphological Analysis in Classes with Language Activities ---In a Clan for Knowledge Acquisition of High School ``Basic Physics''---," JSiSE Research Report, vol. 38, no. 4 , pp. 8-15, 2023.
- Kohta Okahara, Hideyuki Ichihara, Tomoo Inoue, "Analysis and Improvement of the Parallel Implementation of Linear FSMs for Reducing the Latency in Stochastic Computing," IEICE Tech. Repo., vol.123, no.258(VLD), pp. 106-111, 2023.
- Jin-Tsung Wu, Hideyuki Ichihara, Tomoo Inoue, Tong-Yu Hsieh, "A No-reference Test Method for Video Decoders in Object Detection Application," FIIS, 2023.
- Tamaki Kozuma, Qiling Wang, Hideyuki Ichihara, Tomoo Inoue, "Analysis of the Relationship between the Error Recovery and Reliability on Approximate Multipliers ," Tech. Repo., vol. 122, no. 393, pp. 21--26, 2023.
- Tamaki Kozuma, Hideyuki Ichihara, Tomoo Inoue, "Reliability Analysis of Approximate Multipliers with Recovery Schemes," IEICE Technical Report (FIIS-22-567), 2022.
- Mitsuyoshi Ashida, Tomoo Inoue, Hideyuki Ichihara, "A TMR-Based Approximate Corrector for Fail-Operational Systems," IEICE Tech. Report, vol. 121, no. 388, DC2021-70, pp. 33−38, 2022.
- Mitsuyoshi Ashida, Ryoga Mizobata, Hideyuki Ichihara, Tomoo Inoue, "An Experimental Consideration of a Hybrid Approximate Multiplier Design According to the Accuracy Required for Applications," The 22nd IEEE Hiroshima Section Student Symposium, 2020.
- Toya Kani, Nobuaki Seto, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On the Accuracy of Sigmoid Functions in Stochastic-Computing-Based Neural Networks," DA Symposium, pp. 36-43, 2020.
- Toya Kani, Nobuaki Seto, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Study on Hardware Implementation of Sigmoid Functions with Stochastic Computing," FTC Workshop, 2020.
- Norishige Morikawa, Yuri Aono, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Simplification of Multiple-Output Logic Functions for Error-Tolerant Applications Using Don't-Care Extension," FTC workshop, 2020.
- Kazunori Yukihiro, Hideyuki Ichihara, Tomoo Inoue, "Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems," Tech. Repo., pp. 31-36, 2019.
- Hideyuki Ichihara, Yuki Maeda, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue, "Transient Fault Tolerant Design for Stochastic Circuits with Linear Finite State Machines," Functional Integrated Information System, 2019.
- Ryoga Mizobata, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Multipliers with Approximate Full Adders and Compensators for the Required Accuracy of Applications," IEICE Technical Report (FIIS-19-494), pp. 1-6, Mar 2019.
- Hideyuki Ichihara, "Benefits and Challenges of Stochastic Computing Circuits," Proc. IFAT, 2019.
- Yuki Maeda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines ," Tech. Repo., pp. 61-66, 2019.
- Toya Kani, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A Study on the Accuracy of Stochastic Operation for Neural Networks Using Positive/Negative Separation of Products and Approximation of Sigmoid Functions," FTC Technical Report, 2019.
- Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis," IEICE Technical Report (DC2018-45), Vol. 118, No. 335, pp. 137-142, Dec 2018.
- Hideyuki Ichihara, "BENEFITS AND CHALLENGES OF STOCHASTIC COMPUTING CIRCUITS," Proc. of the 2018 IEICE Society Conference, pp. SS25-26, Sep 2018.
- Kazunori Yukihiro, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Performance Degradation Faults of Autonomous Cars Using MATLAB/Simulink," FIIS, Mar 2018.
- Akira Kojima, Naoki Ishikawa, Hideyuki Ichihara, Hiroyuki Inoue, Tomoyuki Ohta, Hiroyasu Obata, Atsushi Kubota, Koichi Shin, Chisa Takano, Shinobu Nagayama, "Development of Experimental Robot and Laboratory Curriculum for Education of Embedded Technology and Network Technology," Proc. 80th National Convention of IPSJ, pp. 373-374, 2018.
- Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "An Improved Algorithm of Peripheral Signal Selection for Stochastic Number Generation," FTC , Jan 2018.
- Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "On Fault Detectability by Scan Chain Testing in RTL Scan Design," FTC Technical Report, Jan 2018.
- Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits," IEICE Tech. Repo., vol. 117, no. 273, VLD2017-47, pp. 115-120, Nov 2017.
- Akira Kojima, Naoki Ishikawa, Hideyuki Ichihara, Hiroyuki Inoue, Tomoyuki Ohta, Hiroyasu Obata, Atsushi Kubota, Koichi Shin, Chisa Takano, Shinobu Nagayama, "Development of Experimental Robot for Education of Embedded Technology and Network Technology," 6th workshop , 2017.
- Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue, "Detection of faults on functional paths in RTL scan circuits by scan chain testing," FIIS-17-461, pp. 1-4, 2017.
- Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application ," IEICE Tech. Repo., vol. 116, no. 478, VLD2016-128, pp. 145-150, Mar 2017.
- Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Architecture of Multiply-Accumulate Operation with Stochastic Iteration ," IEICE Tech. Repo., vol. 116, no. 478, VLD2016-130, pp. 157-162, Mar 2017.
- Seiya Kawashima, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "On a Design of Arithmetic Circuits with Multiple Accuracy Modes and Their Application," Tech. Repo. FIIS, Mar 2017.
- So Shioyama, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Implementation of Mutually Reconfigurable Fault-Tolerant Systems with Zynq SoCs," Tech. Repo. FIIS, Mar 2017.
- Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue, "Impact of operational unit binding on aging-induced degradation in high-level synthesis for asynchronous systems," IEICE Technical Report (DC2016-78), Vol. 116, No. 466, pp. 23-28, Feb 2017.
- Maki Fujiha, Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Random Sequence Generation with Internal Signals of Logic Circuits for Stochastic Computing," FTC workshop, Jan 2017.
- Motoi Fukuda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On State Assignment of Finite State Machines for Soft Error Resilient Stochastic Computing," IEICE technical report, pp. 7-12, Jun 2016.
- Yasutake Mitoh, Seiya Kawashima, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Design and Implementation of Adaptive Cruise Control Systems Based on a Cyber-Physical Model," Tech. Repo. FIIS, Mar 2016.
- Yutaro Ishimori, Seiya Kawashima, Yasutake Mitoh, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "On modeling of cyber-physical systems with dependability," Tech. Repo. FIIS, Mar 2016.
- Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Random Sequences with Internal Signals of Logic Circuits for Stochastic Number Generation," Proc. the IEICE General Conference, Mar 2016.
- Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences," IEICE Tech. Repo., vol. 115, no. 449, DC2015-89, pp. 19-24, Feb 2016.
- Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue, "Compact and Accurate Stochastic Circuits with Shared Random Number Sources," ACSI, Jan 2016.
- Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems ," IEICE Tech. Repo., vol. 115, no. 339, DC2015-56, pp. 147-152, Dec 2015.
- Motoi Fukuda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "Influence of Logical Stuck-at Faults on Accuracy in Stochastic Computing," FTC, Jul 2015.
- Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "On Accuracy and Area of Digital Filter Circuits Based on Stochastic Computing," Functional Integrated Information System, Jun 2015.
- Daiki Sunamori, Takuya Ohishi, Shota Ishii, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "FPGA-based Implementation of Image Processing with Stochastic Computing," Tech. Repo. FIIS, Nov 2013.
- Junpei Kamei, Shigo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A logic simplification algorithm with multiple stuck-at faults for error tolerant application ," IEICE Technical Report (VLD2012-136), Vol. 112, No. 451, pp. 1-6, Mar. 2013.
- Tomoya Inaoka, Junpei Kamei, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, "A study on logic simplification of bus inverting circuits for low power," IEICE Technical Report (FIIS-13-353), pp. 1-6, Mar. 2013.
- Shigo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application ," IEICE Technical Report, Vol. 112, No. 429, pp. 49-54, Feb. 2013.
- Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse," IEICE Technical Report (DC2012-80), Vol. 112, No. 429, pp. 1-6, Feb. 2013.
- Masaaki Sakurada, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Model for Over-testing Alleviation and Its Application to Testing Based on Fault Acceptability," Tech. Report of IEICE, Vol. 112, No. 362, pp. 21-26, Dec. 2012.
- Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis," IEICE Technical Report (DC2012-50), Vol. 112, No. 321, pp. 147-152, Nov. 2012.
- Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse," IEICE Technical Report (DC2012-49), Vol. 112, No. 321, pp. 141-146, Nov. 2012.
- Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test," Tech. Report of IEICE, Vol. 112, No. 102, pp. 15-20, June 2012.
- Junpei Kamei, Shigo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "An efficient procedure of acceptability identification for logic optimization based on acceptable faults," IEICE Technical Report (FIIS-12-337), pp. 1-6, June 2012.
- Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools," IEICE Technical Report (VLD2012-130), Vol. 111, No. 450, pp. 61-66, Mar. 2012.
- Kouta Omobayashi, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "A Design of Low-Power Color Interporation Circuits Based on Color Difference ," IEICE Technical Report (VLD2012-143), Vol. 111, No. 450, pp. 139-144, Mar. 2012.
- Fumiyuki Hafuri, Kenji Ueda, Toshiya Mukai, Hideyuki Ichihara, Tomoo Inoue, "Test Generation Using Boolean Satisfiability Based on Instance Similarity," 13th IEEE Hiroshima Student Symposium, pp. 373-376, Nov. 2011.
- Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, "Modeling Economics of LSI Design and Manufacturing for Selecting Test Design," IEICE Technical Report (DC2011-47), Vol. 111, No. 325, pp. 115-120, Nov 2011.
- Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue, "Effective multi-cycle signatures in testable response analyzers ," IEICE Tech. Rep., Vol. 111, No. 100, pp. 5-10, June 2011.
- Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders ," Technical Report of IEICE, Vol. 110, No. 317, pp. 43-48, Nov. 2010.
- Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths ," IEICE Tech. Rep., Vol. 110, No. 317, pp. 25-30, Nov. 2010.
- Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue, "A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths," IEICE Tech. Rep., Vol. 110, No. 106, pp. 13-18, June 2010.
- Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Class of Partial Thru Testable Sequential Circuits with Multiplexers," IEICE Tech. Rep., Vol. 110, No. 106, pp. 7-11, June 2010.
- Takumi Miyaguchi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, , "A Study on Acceptable Faults in Digital Filters," IEICE Tech. Repo., Vol. 109, No. 416, pp. 63-68, Feb. 2010.
- Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Yield Model with Testability and Repairabilit," IEICE Technical Report, Vol. 109, No. DC-316 , pp. 89-94, Dec. 2009.
- Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing," IEICE Technical Report, Vol. 109, No. 95, pp. 13-18, June 2009.
- Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A design of testable response analyzers in built-in self-test," IEICE Tech. Repo., Vol. 109, No. 11, pp. 37-42, 2009.
- Yusuke Nakashima, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "On the Acceleration of Threshold Test Generation Based on Fault Acceptability," IEICE Technical Report, Vol. 108, No. 431, pp. 1-6, Feb. 2009.
- Kenta Sutoh, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Generation Model for Threshold Testing," IEICE Tech. Rep., Vol. 108, No. 352, pp. 5-10, Dec. 2008.
- Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment," IEICE Tech. Rep., Vol. 108, No. 299, pp. 121-126, Nov. 2008.
- Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance," IEICE Tech. Rep., Vol. 108, No. 299, pp. 127-132, Nov. 2008.
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "A Study on Reliability and Performance of FPGA-Based Fault Tolerant Systems," IEICE Technical Report, Vol. 108, No. 15, pp. 19-24, Apr. 2008.
- Hirotaka Shiomichi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "Synthesis of Fault Secure Datapaths with DFG Restructuring," IEICE Tech. Repo., No. 482, pp. 51-56, Feb. 2008.
- Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue, "An optimization of thru trees for test generation based on acyclical testability," Tech. Report of IEICE, Vol. 107, No. 334, pp. 13-18, Nov. 2007.
- Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue, "A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations," IEICE Technical Report (DC2007-2), Vol. 107, No. DC-17, pp. 7-12, Apr. 2007.
- Syota Takahashi, Ryoji Noji, Hideyuki Ichihara, Tomoo Inoue, "An optimal set of backup contexts for reliable FPGA systems," Proc. the 69th National Convention of IPSJ, No. 1, pp. 109-110, Mar. 2007.
- Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara, "An Entended Class of Sequential Circuits with Acyclical Testability," IEICE Tech. Repo. (DC2006-88), Vol. 106, No. 528, pp. pp.49-54, Feb. 2007.
- Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue, "A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure," IEICE Tech. Rep. (DC2006-42), Vol. 106, No. 390, pp. 23-28, Nov. 2006.
- Yukinori Setohara, Yusuke Nakashima, Hideyuki Ichihara, Tomoo Inoue, "Test Compression/Decompression with the Decoding Function in Multimedia Cores," IEICE Tech. Repo.(DC2006-43), Vol. 106, No. 390, pp. 29-34, Nov. 2006.
- Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue, "A Self-Test of Dynamically Reconfigurable Processors," IEICE Tech. Repo. (DC2006-49), Vol. 106, No. 390, pp. 65-70, Nov. 2006.
- Masashi Yamanaka, Hideyuki Ichihara, Tomoo Inoue, "On the Fault Escape and Yield Loss by Faulty BIST Circuits," Proc. of the 2006 IEICE General Conference, Mar. 2006.
- Go Handa, Naoya Takeuchi, Hideyuki Ichihara, Tomoo Inoue, "A register binding method in high level synthesis for strong testability," IEICE Tech. Rep., Vol. DC2005-72, pp. 1-6, Feb. 2006.
- Yukinori Setohara, Takashi Fujii, Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of Fault Simulation Using FPGAs," , pp. 238-241, Nov. 2005.
- Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue, "An Improvement of a DFT Method Based on Fixed-control Testability by Conflict Avoidance," FIT2005, Sept. 2005.
- Nobuya Oka, Hideyuki Ichihara, Tomoo Inoue, "An Acceleration of a Scheduling Algorithm in High-Level Synthesis for Acyclic Partial Scan," FIT2005, Sept. 2005.
- Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue, "A Reconfigurable Embedded Decompressor for LSI Testing ," , Vol. 105, No. 42, pp. 1-6, May 2005.
- Naoki Okamoto, Hideyuki Ichihara, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "Design for Hierarchical Testability for Reducing Hold Controls," Technical Report of IEICE, Vol. 104, No. 664, pp. 15-20, Feb. 2005.
- Michihiro Shintani, Masakuni Ochi, Hideyuki Ichihara, Tomoo Inoue, "A decompressor with buffer for test compression / decompression," Technical Report of IEICE, Vol. ICD2004, No. 213, pp. 35-40, Jan. 2005.
- Masakuni Ochi, Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, "A Test Vector Ordering for Overhead Reduction of Test Decompressors," Technical report of IEICE, Vol. 103, No. 668, pp. 41-46, Feb. 2004.
- Naoki Okamoto, Hideyuki Ichihara, Tomoo Inoue, Toshinori Hosokawa, Hideo Fujiwara, "An Improvement of the Test Plan Generation Algorithm for Strongly Testable Datapaths," Technical Report of IEICE, Vol. 103, No. 476, pp. 13-18, Nov. 2003.
- Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, "A Test Decompression Scheme Based on Huffman Coding," Proc Electronics, Information and Systems Conference, pp. 602-608, Aug. 2003.
- Toshimasa Ohara, Michihiro Shintani, Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "A Test Compression for Test Application Based on Huffman Coding," Technical Report of IEICE, Vol. 102, No. 658, pp. 67-72, Feb. 2003.
- Michihiro Shintani, Toshimasa Ohara, Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "Test response compression using Huffman coding," Technical Report of IEICE, Vol. VLD2002-88, pp. 35-40, Nov. 2002.
- Hideyuki Ichihara, Tomoo Inoue, Akio Tamura, "Test Generation for Acyclic Sequential Circuits using Combinational ATPG for Single Stuck-at Faults," Technical Report of IEICE, Vol. 100, No. 473, pp. 203-208, Nov. 2000.
- Hideyuki Ichihara, Kozo Kinoshita, "New Redundancy Identification Method on Logic Optimization Using Implication Relation," Technology Reports of Osaka University, Vol. 48, No. 2301-2318, pp. 55-63, Apr. 1998.
- Hideyuki Ichihara, Kozo Kinoshita, "On Acceleration of Logic Circuits Optimization using Implication Relations," Technical Report of IEICE, Vol. 96, No. 519, pp. 57-64, Feb. 1997.